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myson technology MTV048 (rev 0.9) on-screen-display controller for crt/lcd monitor this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. rev 0.9 - 1 - 2001/03/15 features software control for crt/lcd applications. full screen self-test pattern generator with programmable pattern color. on-chip pll circuitry (crt) or external pixel clock input (lcd) up to 150 mhz. horizontal sync input up to 150 khz. programmable horizontal resolutions up to 1524 dots per display line. full screen display consists of 15 (rows) by 30 (columns). 12x16 or 12x18 dot matrix selection. a total of 384 fonts including 360 standard fonts, 16 multi-color fonts and 8 user fonts. 8 color selections for character foreground, background and window color. character button boxes with programmable box length. character bordering, shadowing and blinking effect for display. full-screen character double width control. double character height and/or width control per row. programmable positioning for display screen center. row to row spacing control per row to avoid expansion distortion. 4 programmable background windows with multi-level operation and programmable shadow width/height/color. software clear bit for full-screen erasing. programmable adaptive approach to handle h, v sync collision automatically by hardware. fade-in/fade-out or blend-in/blend-out effects. compatible with spi bus or i 2 c interface with address 7ah (slave address is mask option). 5v or 3.3v power supply. 16-pin pdip/sop package. general description MTV048 is designed for monitor applications to display built-in fonts onto monitor screens. the display operation occurs by transferring data and controls information from the micro controller to ram through a serial data interface. it can execute a full-screen display automatically, as well as specific functions such as character background, bordering, shadowing, blinking, double height and width, font-by-font color control, button boxes, frame positioning, frame size control by character height and row-to-row spacing, horizontal display resolution, full- screen erasing, fade-in/fade-out effect, windowing effect, shadowing on window and full-screen self-test pattern generator. MTV048 provides 384 fonts including 360 standard fonts, 16 multi-color fonts and 8 user fonts and 2 font sizes, 12x16 or 12x18 for more efficacious applications. the full osd menu is formed by 15 rows x 30 columns, which can be positioned anywhere on the monitor screen by changing vertical or horizontal delay. block diagram serial data interface vertical display control horizontal display control phase lock loop display & row control registers (ram) fonts rom & user fonts ram color encoder windows & frame control luminance & border generator hflb vflb vco rp ssb sck sda rout gout bout fbkg int 9 romaddr r/wen 8 data vclk row column 9 ramaddr luma shadow window
myson technology MTV048 (rev 0.9) rev 0.9 - 2 - 2001/03/15 1.0 pin connection 2.0 pin descriptions name i/o pin no. descriptions vss - 1 analog ground. this ground pin is used for internal analog circuitry. vco / xin i/o 2 voltage control oscillator (bit lcd = 0). this pin is used to control the internal oscil lator frequency by dc voltage input from external low pass filter. pixel clock input (bit lcd = 1). this is a clock input pin. MTV048 can be driven by an external pixel clock source for all the logic inside. the frequency of xin must be the integral time of pin hflb. rp / nc i/o 3 bias resistor (bit lcd = 0). the bias resistor is used to regulate the appropriate bias current for internal oscillator to resonate at specific dot frequency. no connection (bit lcd = 1). vdda - 4 analog power supply. positive 5v / 3.3v dc supply for internal analog cir cuitry. and a 0.1uf decoupling capacitor should be connected across to vdda and vssa. hflb i 5 horizontal input. this pin is used to input the horizontal synchronizing signal. it is a leading edge triggered and has an internal pull-up resistor. ssb i 6 serial interface enable. it is used to enable the serial data and is also used to select the operation of i 2 c or spi bus. if this pin is left floating, i 2 c bus would be enabled. otherwise the spi bus is enabled. sda i 7 serial data input. the external data transfer through this pin to internal display registers and control registers. it has an internal pull- up resistor. sck i 8 serial clock input. the clock-input pin is used to synchronize the data transfer. it has an internal pull-up resistor. vdd - 9 digital power supply. positive 5v / 3.3v dc supply for internal digital circuitry and a 0.1uf decoupling capacitor should be connected across to vdd and vss. vflb i 10 vertical input. this pin is used to input the vertical synchronizing signal. it is leading triggered and has an internal pull-up resistor. vssa vco/xin vdda hflb ssb sda sck rp/nc vdd vss rout gout fbkg v33cap bout vflb MTV048n-xx 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
myson technology MTV048 (rev 0.9) rev 0.9 - 3 - 2001/03/15 v33cap i/o 11 3.3v regulator capacitor connection. connect a decoupling capacitor to vss pin when dc supply = 5v, or connect to 3.3v directly when dc supply = 3.3v. fbkg o 12 fast blanking output. it is used to cut off external r, g, b signals of vga while this chip is displaying characters or windows. bout o 13 blue color output. it is a blue color video signal output. and it is a dac output if bit lcd = 0 or cmos output if bit lcd =1. gout o 14 green color output. it is a green color video signal output. and it is a dac output if bit lcd = 0 or cmos output if bit lcd =1. rout o 15 red color output. it is a red color video signal output. and it is a dac output if bit lcd = 0 or cmos output if bit lcd =1. vss - 16 digital ground. this ground pin is used for internal digital circuitry. 3.0 functional descriptions 3.1 serial data interface the serial data interface receives data transmitted from an external controller. there are 2 types of buses, which can be accessed through the serial data interface. one is spi bus and the other is i 2 c bus. 3.1.1 spi bus while ssb pin is pulled to "high" or "low" level, the spi bus operation is selected. and a valid transmission should start pulling ssb to "low" level, enabling MTV048 to receiving mode, and retain at "low" level till the last cycle for a complete data packet transfer. the protocol is shown in figure 1. figure 1. data transmission protocol (spi) there are three transmission formats, shown as below: format (a) r - c - d ? r - c - d ? r - c - d ? .. format (b) r - c - d ? c - d ? c - d ? c - d ? .. format (c) r - c - d ? d ? d ? d ? d ? d ? .. where r=row address, c=column address, d=display data 3.1.2 i 2 c bus i 2 c bus operation is only selected when ssb pin is left floating. and a valid transmission should start writing the slave address 7ah to MTV048. the protocol is shown in figure?2. first byte last byte ssb sck sda msb lsb
myson technology MTV048 (rev 0.9) rev 0.9 - 4 - 2001/03/15 figure 2. data transmission protocol (i 2 c) there are three transmission formats for i 2 c write mode, shown as below: format (a) s - r - c - d ? r - c - d ? r - c - d ? .. format (b) s - r - c - d ? c - d ? c - d ? c - d ? .. format (c) s - r - c - d ? d ? d ? d ? d ? d ? .. where s=slave address, r=row address, c=column address, d=display data each arbitrary length of data packet consists of 3 portions viz, row address (r), column address (c), and display data (d). format (a) is suitable for updating small amount of data, which will be allocated with a different row address and column address. format (b) is recommended for updating data that has the same row address but a different column address. massive data updating or full screen data change should use format (c) to increase transmission efficiency. the row and column address will be incremented automatically when the for mat (c) is applied. furthermore, the undefined locations in display or user fonts ram should be filled with dummy data. table 1. the configuration of transmission formats address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 format row 1 0 0 r4 r3 r2 r1 r0 a,b,c column ab 0 0 d8 c4 c3 c2 c1 c0 a,b column c 0 1 d8 c4 c3 c2 c1 c0 c address bytes of display reg. data d7 d6 d5 d4 d3 d2 d1 d0 a,b,c row 1 0 1 r4 r3 r2 r1 r0 a,b,c column ab 0 0 x c4 c3 c2 c1 c0 a,b column c 0 1 x c4 c3 c2 c1 c0 c attribute bytes of display reg. data d7 d6 d5 d4 d3 d2 d1 d0 a,b,c row 1 1 - - - r2 r1 r0 a,b,c column ab 0 0 c5 c4 c3 c2 c1 c0 a,b column c 0 1 c5 c4 c3 c2 c1 c0 c user fonts data d7 d6 d5 d4 d3 d2 d1 d0 a,b,c there are 3 types of data, which should be accessed through the serial data interface. one is address bytes of dis play registers, another is attribute bytes of display registers, and the other is user fonts ram data . the protocols are all the same except the bit6 and bit5 of row address and the bit5 of column address. the msb (b7) is used to distinguish row and column addresses when transferring data from external controller. the bit6 of row address is used to distinguish display registers and user fonts ram data and the bit6 of column address is used to differentiate the column address for format (a), (b) and format (c) respectively. bit5 of row address for display register is used to distinguish address byte when it is set to "0" and attribute byte when it is set to "1". and at address bytes, bit5 of column address is the msb (bit8) and data bytes are the 8 lsb (bit7~bit0) of display fonts address to save half mcu memory for true 392 fonts display. so each one of the 384 fonts can be displayed at the same time. see table 1 . and for format (c), since d8 is filled while program column address of address bytes, the continued data will be the same bank of upper 128 fonts or lower 256 fonts until program column address is of address bytes again. sck sda first byte start ack second byte last byte ack stop b7 b6 b0 b7 b0
myson technology MTV048 (rev 0.9) rev 0.9 - 5 - 2001/03/15 the data transmission is permitted to change from format (a) to format (b) and (c ), or from format (b) to format (a), but not from format (c) back to format (a) and (b). the alternation between transmission formats is config ured as the state diagram shown in figure?3 . figure 3. transmission state diagram 3.2 address bus administrator the administrator manages bus address arbitration of internal registers or user fonts ram during external data write in. the external data write through serial data interface to registers must be synchronized by inter- nal display timing. in addition, the administrator also provides automatic increment to address bus when exter nal write using format (c). 3.3 vertical display control the vertical display control can generate different vertical display sizes for most display standards in current monitors. the vertical display size is calculated with the information of double character height bit ( chs), verti cal display height control register (ch6-ch0). the algor ithms of repeating character line display are shown as table 2 and table 3. the range of programmable vertical size is 270 lines to 2130 lines maximum. the vertical display center for full screen display could be figured out according to the information of vertical starting position register (vertd) and vflb input. the vertical delay starting from the leading edge of vflb is calculated by using the following equation: vertical delay time = ( vertd * 4 + 1 ) * h where h = one horizontal line display time table 2. repeat line weight of character ch6 ? ch0 repeat line weight ch6, ch5 = 11 +18*3 ch6, ch5 = 10 +18*2 ch6, ch5 = 0x +18 ch4 = 1 +16 ch3 = 1 +8 ch2 = 1 +4 ch1 = 1 +2 ch0 = 1 +1
myson technology MTV048 (rev 0.9) rev 0.9 - 6 - 2001/03/15 table 3. repeat line number of character repeat line # repeat line weight 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +1 - - - - - - - - v - - - - - - - - - +2 - - - - v - - - - - - - v - - - - - +4 - - v - - - v - - - v - - - v - - - +8 - v - v - v - v - v - v - v - v - - +16 - v v v v v v v v v v v v v v v v - +17 v v v v v v v v v v v v v v v v v - +18 v v v v v v v v v v v v v v v v v v note: ? v ? means the n th line in the character would be repeated once, while ? - ? means the n th line in the character would not be repeated. 3.4 horizontal display control the horizontal display control is used to generate control timing for horizontal display based on double char- acter width bit (cws), horizontal positioning register (hord), horizontal resolution register (horr), and hflb input. a horizontal display line consists of (horr*12) dots which include 360 dots for 30 display char- acters and the remaining dots for blank region. the horizontal delay starting from hflb leading edge is calcu lated by using the following equation: for crt: horizontal delay time = ( hord * 6 + 49) * p - phase error detection pulse width where p = one pixel display time = one horizontal line display time / (horr*12) for lcd: horizontal delay time = ( hord * 6 + 49) * p where p = one xin pixel dis play time 3.5 phase lock loop (pll) on-chip pll generates system clock timing (vclk) by tracking the input hflb and horizontal resolution reg- ister (horr). the frequency of vclk is determined by the following equation: vclk freq. = hflb freq. * horr * 12 the vclk frequency ranges from 6mhz to 150mhz selected by (vco1, vco0). in addition, when hflb input is not present to MTV048, the pll will generate a specific system clock, approximately 2.5mhz, by a built-in oscillator to ensure data integrity. 3.6 display & row control registers the internal ram contains display and row control registers. the display registers have 450 locations, which are allocated between (row 0, column 0) to (row 14, column 29), as shown in figure?4 . each display register has its corresponding character address on address byte , its corresponding background color, 1 blink bit and its corresponding color bits on attribute bytes. the row control register is allocated at column 30 for row 0 to row 14 , it is used to set character size to each respective row. if double width character is chosen, only even column characters could be displayed on screen and the odd column characters will be hidden.
myson technology MTV048 (rev 0.9) rev 0.9 - 7 - 2001/03/15 column # row # 0 1 28 29 30 31 0 1 13 14 character address bytes of display registers row ctrl reg r e s e r v e d figure 4. address bytes of display registers memory map column # row # 0 1 28 29 30 31 0 1 13 14 character attribute bytes of display registers reserved column # 0 11 12 22 23 31 row 15 window1 ~ window4 frame ctrl reg. reserved column # 0 1 2 4 5 31 row 16 window shadow color frame ctrl reg. reserved figure 5. attribute bytes of display registers memory map address bytes: address registers, (row 0 ~ 14, column 0 ~ 29), b8 b7 b6 b5 b4 b3 b2 b1 b0 craddr msb lsb craddr - define osd character address from address 0 to 383. = 0 ~ 359 t 360 standard rom fonts. = 360 ~ 367 t 8 user fonts. = 368 ~ 383 t 16 multi-color rom fonts. row control registers (row 0 ~ 14, column 30), b7 b6 b5 b4 b3 b2 b1 b0 - - - box - - chs cws box - select bgr, bgg, bgb or box2, box1, box0 of attributes bytes to the respective row. = 0 t background color bits bgr, bgg, bgb are selected. = 1 t button boxes bits box2, box1, box0 are selected. chs - define double height character to the respective row. cws - define double width character to the respective row. if double width character is chosen, only even
myson technology MTV048 (rev 0.9) rev 0.9 - 8 - 2001/03/15 column characters could be displayed on screen and the odd column characters will be hidden. attribute bytes: attribute registers, (row 0 ~ 14, column 0 ~ 29), b7 b6 b5 b4 b3 b2 b1 b0 - bgr/box2 bgg/box1 bgb/box0 blink r g b bgr, bgg, bgb : these three bits define the background color for their individual relative address characters. if these three bits are set to (0, 0, 0), no background will be shown (transparent). therefore, a total of 7 background colors can be selected. box2-0 - select the character button boxes format of its relative address character. = 0, 0, 0 t button boxes is disabled. = 1, 0, 0 t start of depressed button box which is more than 1 character button box. = 1, 0, 1 t start of depressed button box which is only 1 character button box. = 1, 1, 0 t start of raised button box which is more than 1 character button box. = 1, 1, 1 t start of raised button box which is only 1 character button box. = 0, 1, 0 t middle of button box. = 0, 0, 1 t end of button box. blink = 1 t enable blink effect for its relative address character. and the blinking is alternate per 32 vertical frames. = 0 t disable blink effect for its relative address character. r, g, b - these three bits are used to specify their individual relative address character foreground color. 3.7 character button boxes generator there are 4 character button box generators to generate 4 different types of button boxes including depressed button box with only 1 character, depressed button box with more than 1 character, raised button box with only 1 character, and raised button box with more than 1 character. the button boxes format is defined by (box2, box1, box0) bits of attribute bytes. and these bits are described as below: 1). (1, x, x) means the start of character button box, and than box1-0 bits define the format of button box. 2). (0, 1, 0) means the middle of character button box. 3). (0, 0, 1) means the end of character button box. the length of button box is also software control by (box2, box1, box0) bits. for example, if there is 1 raised button box whose length is equal to 6 characters, these box2-0 bits will be (1, 1, 0), (0, 1, 0), (0, 1, 0), (0, 1, 0), (0, 1, 0), (0, 0, 1). and if there is 1 depressed button box whose length is equal to 4 characters, these box2-0 bits will be (1, 0, 0), (0, 1, 0), (0, 1, 0), (0, 0, 1). that is, (0, 1, 0) command's number defines the button box length. and only 1 byte, the attribute byte of button box start character, should be modified when changing button box type from raised button to depressed button, or vice versa. this is very easy and useful for software programming. 3.8 character rom MTV048 character rom contains 384 characters and symbols including 360 standard fonts, 8 user fonts and 16 multi-color fonts. the 360 standard fonts are located from address 0 to 359. the 8 user fonts are located from address 360 to 367.and the 16 multi-color fonts are located from address 368 to 383. each character and symbol consists of 12x18 dots matrix.
myson technology MTV048 (rev 0.9) rev 0.9 - 9 - 2001/03/15 figure 6. character button boxes 3.9 multi-color font the color fonts comprise three different r, g, b fonts. when the code of color font is accessed, the separate r/g/b dot pattern is output to corresponding r/g/b outputs. see figure?7 for the sample displayed color font. note: no black color can defined in color font, black window underline the color font can make the dots become black in color. figure 7. example of multi-color font magenta green blue cyan r g b b2~b0 = 1, 1, 1 1, 1, 0 0, 0, 1 1, 1, 0 0, 1, 0 0, 1, 0 0, 0, 1 raised button boxes box2-0 = 1, 0, 1 1, 0, 0 0, 0, 1 1, 0, 0 0, 1, 0 0, 1, 0 0, 0, 1 depressed button boxes
myson technology MTV048 (rev 0.9) rev 0.9 - 10 - 2001/03/15 table 4. the multi-color font color selection r g b background color 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1 3.10 user fonts ram the user fonts ram have 288 locations, which are allocated between (row 0, column 0) to (row 7, column 35) to specify 8 user programmable fonts, as shown in figure 6. each user programmable font consists of 12x18 dot matrix which data are stored in 36 bytes registers. and each line of dot matrix consists of 2 bytes data, which include 4 dummy bits as shown in figure 7 and figure 8. for example, font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to column 35, etc. row # column # 0 1 34 35 36 63 0 1 6 7 user fonts ram reserved figure 6. user fonts ram memory map nth byte (n+1)th byte 12 bits for one row data of font dot matrix dummy bits rightmost dot of font where n=even number b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 leftmost dot of font figure 7. data format of user font dot matrix figure 8. example of user font programming column # data column# data 0 00h 1 00h 2 00h 3 00h 4 3fh 5 00h 6 3fh 7 80h 8 31h 9 c0h 10 30h 11 c0h 12 30h 13 c0h 14 31h 15 c0h 16 3fh 17 80h 18 3fh 19 00h 20 30h 21 00h 22 30h 23 00h 24 30h 25 00h 26 30h 27 00h 28 30h 29 00h 30 30h 31 00h 32 00h 33 00h 34 00h 35 00h
myson technology MTV048 (rev 0.9) rev 0.9 - 11 - 2001/03/15 3.11 luminance & border generator there are 3 shift registers included in the design which can shift out of luminance and border dots to color encoder. the bordering and shadowing feature is configured in this block. for bordering effect, the character will be enveloped with blackedge on four sides. for shadowing effect, the character is enveloped with blackedge for right and bottom sides only. 3.12 window and frame control the display frame position is completely controlled by the contents of vertd and hord. the window size and position control are specified in column 0 to 11 on row 15 of memory map, as shown in figure?5 . window 1 has the highest priority, and window 4 is the least, when two windows are overlapping. more detailed infor mation is described as follows: 1. window control registers, row 15 b7 b6 b5 b4 b3 b2 b1 b0 column 0,3,6 or 9 row start addr msb lsb row end addr msb lsb b7 b6 b5 b4 b3 b2 b1 b0 column 1,4,7 or 10 column start addr msb lsb wen - wshd b7 b6 b5 b4 b3 b2 b1 b0 column 2,5,8 or 11 column end addr msb lsb r g b start(end) addr - these addresses are used to specify the window size. it should be noted that when the start address is greater than the end address, the window would be disabled. wen - enable the relative background window display. wshd - enable shadowing on the relative window. r, g, b - specify the color of the relative background window. 2. frame control registers, row 15 b7 b6 b5 b4 b3 b2 b1 b0 column 12 vertd msb lsb vertd - specify the starting position for vertical display. the total steps are 256, and the increment of each step is 4 horizontal display lines. the initial value is 4 after power up. b7 b6 b5 b4 b3 b2 b1 b0 column 13 hord msb lsb hord - define the starting position for horizontal display. the total steps are 256, and the increment of each step is 6 dots. the initial value is 15 after power up.
myson technology MTV048 (rev 0.9) rev 0.9 - 12 - 2001/03/15 b7 b6 b5 b4 b3 b2 b1 b0 column 14 - ch6 ch5 ch4 ch3 ch2 ch1 ch0 ch6-ch0 - define the character vertical height, the height is programmable from 18 to 71 lines. the character vertical height is at least 18 lines if the content of ch6-ch0 is less than 18. for example, when the content is " 2 ", the character vertical height is regarded as equal to 20 lines. and if the con tent of ch4-ch0 is greater than or equal to 18, it will be regarded as equal to 17. see table 2 and table 3 for detail description of this operation. b7 b6 b5 b4 b3 b2 b1 b0 column 15 - horr msb lsb (this byte is used only for crt monitor application.) horr - specify the resolution of a horizontal display line, and the increment of each step is 12 dots. that is, the pixels' number per h line equal to horr*12. it is recommended that horr should be greater than or equal to 36 and smaller than 150m / (hfreq*12). the initial value is 40 after power up. b7 b6 b5 b4 b3 b2 b1 b0 column 16 - - - rspace msb lsb rspace - define the row to row spacing in unit of horizontal line. that is, extra rspace horizontal lines will be appended below each display row, and the maximum space is 31 lines. the initial value is 0 after power up. b7 b6 b5 b4 b3 b2 b1 b0 column 17 osden bsen shadow fben blend winclr ramclr fbkgc osden - activate the osd operation when this bit is set to "1". the initial value is 0 after power up. bsen - enable the bordering and shadowing effect. shadow - activate the shadowing effect if this bit is set, otherwise the bordering is chosen. fben - enable the fade-in/fade-out or blend-in/blend-out effect when osd is turned on from off state or vice versa. blend - fade-in/fade-out or blend-in/blend-out effect select bit. activate the blend-in/blend-out effect if this bit is set, otherwise the fade-in/fade-out function is chosen. this function roughly takes about 0.5 second to fully display the whole menu or to disappear completely. wenclr - clear all wen bits of window control registers when this bit is set to "1". the initial value is 0 after power up. ramclr - clear all address bytes, bgr, bgg, bgb and blink bits of display registers when this bit is set to "1". the initial value is 0 after power up. fbkgc - define the output configuration for fbkg pin. when it is set to "0", the fbkg outputs high during the dis playing of characters or windows, otherwise, it outputs high only during the displaying of character. b7 b6 b5 b4 b3 b2 b1 b0 column 18 tric fss - selvcl/dwe hsp vsp vco1/- vco0/-
myson technology MTV048 (rev 0.9) rev 0.9 - 13 - 2001/03/15 (selvcl, vco1, vco0 bits are used for crt monitor applications only.) (dwe bit is used only for lcd monitor applications.) tric - define the driving state of output pins rout, gout, bout and fbkg when osd is disabled. that is, while osd is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are in high impedance state. the initial value is 0 after power up. fss - font size selection. = 1 t 12x18 font size is selected. = 0 t 12x16 font size is selected. figure 8. 12x18 and 12x16 fonts selvcl - enable auto detection for horizontal and vertical syncs input edge distortion to avoid unstable vsync leading mismatch with hsync signal while the bit is set to "1". the initial value is 0 after power up. hsp - = 1 t accept positive polarity hsync input. = 0 t accept negative polarity hsync input. vsp - = 1 t accept positive polarity vsync input. = 0 t accept negative polarity vsync input. vco1, vco0 - select the appropriate curve partitions of vco frequency to voltage based on hflb input and horizontal resolution register (horr). and there are different curve partitions based on differ ent application resi ster value on pin 3 (pin rp) as below: ( i) 5.6k ohm: (ii) 3.3k ohm: = (0, 0) t 6mhz < pixel rate < 24mhz = (0, 0) t 6mhz < pixel rate < 28mhz = (0, 1) t 24mhz < pixel rate < 48mhz = (0, 1) t 28mhz < pixel rate < 56mhz = (1, 0) t 48mhz < pixel rate < 96mhz = (1, 0) t 56mhz < pixel rate < 112mhz = (1, 1) t 96mhz < pixel rate < 128mhz = (1, 1) t 112mhz < pixel rate < 150mhz where pixel rate = vclk freq = hflb freq * horr * 12 the initial value is (0, 0) after power up. notes: 1. that is, if horr is specified and rp resister = 3.3k ohm, then (vco1, vco0) = (0, 0), if 6000/(horr * 12) < hflb freq (khz) < 28000/(horr * 12) = (0, 1), if 28000/(horr * 12) < hflb freq (khz) < 56000/(horr * 12) = (1, 0), if 56000/(horr * 12) < hflb freq (khz) < 112000/(horr * 12) = (1, 1), if 112000/(h orr * 12) < hflb freq (khz) < 150000/(horr * 12) 2. it is necessary to wait for the pll to become stable while (i) the horr register is changed; (ii) the (vco1, vco0) bits is changed; (iii) the horizontal signal (hflb) is changed. 3. when pll is unstable, do not write data in any address except column 15,17,18 of row 15. if data is written in any other address, a malfunction may occur. fonts designed to be 12x18 display 12x16 display if fss=0; first and last lines omitted
myson technology MTV048 (rev 0.9) rev 0.9 - 14 - 2001/03/15 b7 b6 b5 b4 b3 b2 b1 b0 column 19 - - - - - csr csg csb csr, csg, csb - define the color of bordering or shadowing on characters. the initial value is (0, 0, 0) after power up. b7 b6 b5 b4 b3 b2 b1 b0 column 20 fsw - - - - fsr fsg fsb fsw - enable full screen self-test pattern and force the fbkg pin output to high to disable video rgb while this bit is set to "1". the self-test pattern's color is determined by (fsr, fsg, fsb) bits. fsr, fsg, fsb - define the color of full screen self-test pattern. b7 b6 b5 b4 b3 b2 b1 b0 column 21 ww41 ww40 ww31 ww30 ww21 ww20 ww11 ww10 ww41, ww40 - determine the shadow width of window 4 when wshd bit of window 4 is enabled. please refer to the table below for more details. (ww41, ww40) (0, 0) (0, 1) (1, 0) (1, 1) shadow width (unit in pixel) 2 4 6 8 ww31, ww30 - determine the shadow width of window 3 when wshd bit of window 3 is enabled. ww21, ww20 - determine the shadow width of window 2 when wshd bit of window 2 is enabled. ww11, ww10 - determine the shadow width of window 1 when wshd bit of window 1 is enabled. b7 b6 b5 b4 b3 b2 b1 b0 column 22 wh41 wh40 wh31 wh30 wh21 wh20 wh11 wh10 wh41, wh40 - determine the shadow height of window 4 when wshd bit of window 4 is enabled. please refer to the table below for more details. (wh41, wh40) (0, 0) (0, 1) (1, 0) (1, 1) shadow height (unit in line) 2 4 6 8 wh31, wh30 - determine the shadow height of window 3 when wshd bit of window 3 is enabled. wh21, wh20 - determine the shadow height of window 2 when wshd bit of window 2 is enabled. wh11, wh10 - determine the shadow height of window 1 when wsh d bit of window 1 is enabled. figure 9. character bordering and shadowing and shadowing on window note: m and n are defined by the registers of winsw and winsh. n horizontal lines m pixels m pixels n horizontal lines bordering shadowing
myson technology MTV048 (rev 0.9) rev 0.9 - 15 - 2001/03/15 3.13 color encoder the decoder generates the video output to rout, gout and bout by integrating window color, border blackedge, luminance output and color selection output (r, g, b) to form the desired video outputs. column 23 ~ column 31 : reserved. note : the register located at column 31 of row 15 is reserved for the testing. do not program this byte anytime in normal operation. row 16 b7 b6 b5 b4 b3 b2 b1 b0 column 0 - r1 g1 b1 - r2 g2 b2 r1, g1, b1 - define the shadow color of window 1. the initial value is (0, 0, 0) after power up. r2, g2, b2 - define the shadow color of window 2. the initial value is (0, 0, 0) after power up. b7 b6 b5 b4 b3 b2 b1 b0 column 1 - r3 g3 b3 - r4 g4 b4 r3, g3, b3 - define the shadow color of window 3. the initial value is (0, 0, 0) after power up. r4, g4, b4 - define the shadow color of window 4. the initial value is (0, 0, 0) after power up. b7 b6 b5 b4 b3 b2 b1 b0 column 2 - - - - - d2 d1 d0 (this byte is used only for lcd monitor application.) d3-d0 - these 4 bits define the propagation delay of rout, gout, bout, fbkg and int outputs to pin xin input falling edge control registers. please refer to figure 12 and table 8. figure 12. output and hflb timing to pixel clock xin t pd osd output t pd t setup t hold hflb internal clk
myson technology MTV048 (rev 0.9) rev 0.9 - 16 - 2001/03/15 table 7. output timing to pixel clock symbol (d2, d1, d0) min. typ. max. unit t pd 0 1 2 3 4 5 6 7 - - - - - - - - tbd tbd tbd tbd tbd tbd tbd tbd - - - - - - - - ns ns ns ns ns ns ns ns column 3 : reserved. b7 b6 b5 b4 b3 b2 b1 b0 column 4 lcd - id5 id4 id3 id2 id1 id0 lcd - osd application selection. = 1 t lcd monitor application selected. the 2nd and 3rd pins are xin, nc. = 0 t crt monitor application selected. the 2nd and 3rd pins are vco, rp. after this bit is changed, the whole chip circuit will be reset to default value except this byte. so this bit also can work as software reset bit. the initial value is 0 after power up. id5-id0 - lcd bit identify bits. lcd bit can be updated to "1" only when id5-id0 = (0, 1, 0, 1, 0, 1). and lcd bit can be updated to "0" only when id5-id0 = (1, 0, 1, 0, 1, 0). column 6 ~ column 31 : reserved.
myson technology MTV048 (rev 0.9) rev 0.9 - 17 - 2001/03/15 4.0 absolute maximum ratings dc supply voltage (vdd ,vdda) -0.3 to +7 v voltage with respect to ground -0.3 to vdd+0.3 v storage temperature -65 to +150 o c ambient operating temperature 0 to +70 o c 5.0 operating conditions dc supply voltage (vdd ,vdda) +4.75 to +5.25 v operating temperature 0 to +70 o c 6.0 electrical characteristics (under operating conditions) symbol parameter conditions (notes) min. max. units input high voltage (pin hflb, vflb, sda, sck) - 0.6 * vdd vdd+0.3 v v ih input high voltage (pin ssb) 0.7 * vdd vdd+0.3 v input low voltage (pin hflb, vflb, sda, sck) - vss-0.3 0.25 * vdd v v il input low voltage (pin ssb) - vss-0.3 0.2 * vdd v v oh output high voltage i oh 3 -5 ma vdd-0.8 - v v ol output low voltage i ol 5 ma - 0.5 v v odl open drain output low voltage 5 ma 3 i odl - 0.5 v i cc operating current pixel rate=96mhz i load = 0ua - 25 ma i sb standby current vin = vdd, i load = 0ua - 12 ma 7.0 switching characteristic (under operating conditions) symbol parameter min. typ. max. units f hflb hflb input frequency 15 - 150 khz t r output rise time - - 5 ns t f output fall time - - 5 ns t bcsu ssb to sck set up time 200 - - ns t bch ssb to sck hold time 100 - - ns t dcsu sda to sck set up time 200 - - ns t dch sda to sck hold time 100 - - ns t sckh sck high time 500 - - ns t sckl sck low time 500 - - ns t su:sta start condition setup time 500 - - ns t hd:sta start condition hold time 500 - - ns t su:sto stop condition setup time 500 - - ns t hd:sto stop condition hold time 500 - - ns
myson technology MTV048 (rev 0.9) rev 0.9 - 18 - 2001/03/15 8.0 timing diagrams figure 11. data interface timing (spi) figure 12. data interface timing (i 2 c) sck ssb sda t sckl t sckh t bcsu t dcsu t dch t bch t sckh t su:sta t hd:sta t sckl t dcsu t dch t hd:sto t su:sto sck sda
myson technology MTV048 (rev 0.9) rev 0.9 - 19 - 2001/03/15 9.0 package dimension 9.1 16 pin pdip 300mil 9.2 16 pin sop 300mil 0.406 +/-0.013 0.295 +/-0.004 0.406 +/-0.008 0.091 0.098 +/-0.006 0.016 +/-0.004 0.0501 (4x) 0.028 +0.022 /-0.013 0.015x45 7(4x)

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